The present invention generally relates to a 3D semiconductor package, and more particularly to power distribution throughout the 3D semiconductor package.
New integrated circuit technologies include three-dimensional integrated circuits also known as a three-dimensional semiconductor package. One type of 3D semiconductor package can include two or more layers of active electronic components stacked vertically and electrically joined with some combination of through-substrate vias and solder bumps. The 3D semiconductor package can provide numerous benefits such as increased package density yielding a smaller footprint, and improved bandwidth due to the short connection lengths made possible by the use of through-substrate vias.
One example of a 3D semiconductor package may include a main die, a die stack, a laminate substrate, and a printed circuit board (PCB). The die stack may be electrically coupled to the main die, the main die may be electrically coupled to the laminate substrate, and the laminate substrate may be electrically coupled to the PCB. In some cases the main die and the laminate substrate may be joined such that the die stack extends into a recess in the laminate substrate.
In the above example, power may be distributed from the PCB to the die stack through the laminate substrate and the main die. More specifically, power to a topmost chip, or a last chip, of the die stack must traverse numerous connections from the PCB to the laminate substrate, from the laminate substrate to the main die, and then from the main die through the multiple chips of the die stack. This configuration may result in a voltage drop and power delivery to the topmost chip of the die stack may suffer.